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Solution (Morris Mano Book) - Computer System Architecture (CAO) notes for Computer Science Engineering (CSE) is made by best teachers who have written some of the best books of Computer Science Engineering (CSE). It has gotten 37405 views and also has 4.8 rating. You can download Free Solution (Morris Mano Book) - Computer System Architecture (CAO) pdf from EduRev by using search above. You can also find Solution (Morris Mano Book) - Computer System Architecture (CAO) ppt and other Computer Science Engineering (CSE) slides as well. If you want Solution (Morris Mano Book) - Computer System Architecture (CAO) Tests & Videos, you can search for the same too. Computer Science Engineering (CSE) Solution (Morris Mano Book) - Computer System Architecture (CAO) Summary and Exercise are very important for perfect preparation. You can see some Solution (Morris Mano Book) - Computer System Architecture (CAO) sample questions with examples at the bottom of this page. Complete Solution (Morris Mano Book) - Computer System Architecture (CAO) chapter (including extra questions, long questions, short questions, mcq) can be found on EduRev, you can check out Computer Science Engineering (CSE) lecture & lessons summary in the same course for Computer Science Engineering (CSE) Syllabus. EduRev is like a wikipedia just for education and the Solution (Morris Mano Book) - Computer System Architecture (CAO) images and diagram are even better than Byjus! Do check out the sample questions of Solution (Morris Mano Book) - Computer System Architecture (CAO) for Computer Science Engineering (CSE), the answers and examples explain the meaning of chapter in the best manner. This is your solution of Solution (Morris Mano Book) - Computer System Architecture (CAO) search giving you solved answers for the same. To Study Solution (Morris Mano Book) - Computer System Architecture (CAO) for Computer Science Engineering (CSE) this is your one stop solution.

Nov 25, 2013  Solution Manual Of Digital Logic And Computer Design 4th Ed Morris Mano. Internet Archive HTML5 Uploader 1.4.2. Plus-circle Add Review. PDF download. Download 1 file. SINGLE PAGE PROCESSED JP2 ZIP download. Download 1 file. Morris Mano Solutions.pdf - Free download Ebook, Handbook, Textbook, User Guide PDF files on the internet quickly and easily.

1 SOLUTIONS MANUAL DIGITAL DESIGN WITH AN INTRODUCTION TO THE VERILOG HDL Fifth Edition M. MORRIS MANO Professor Emeritus California State University, Los Angeles MICHAEL D. CILETTI Professor Emeritus University of Colorado, Colorado Springs International Edition contributions by B.R Chandavarkar Assistant Professor, Department of Computer Science and Engineering National Institute of Technology Karnataka, SurathkalDigital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.


2CHAPTER 11.1 Base 10 : 10 11 12 13 14 15 16 17 18 19 20 21 22 Octal : 12 13 14 15 16 17 20 21 22 23 24 25 26 Hex : A B C D E F 10 11 12 13 14 15 16 Base 12 : A B 10 11 12 13 14 15 16 17 18 19 1A Base 10 : 23 24 25 26 27 28 29 30 31 32 Octal : 27 30 31 32 33 34 35 36 37 40 Hex : 17 18 19 1A 1B 1C 1D 1E 1F 20 Base 12 : 1B 20 21 22 23 24 25 26 27 281.2 (a) 16,384(b) 33,554,432(c) 3,435,973,8371.3 (a) (432)5 = 4 × 52 + 3 × 51 + 2 × 50 = 100 + 15 + 2 = (117)10(b) (A98)12 = 10 × 122 + 9 × 121 + 8 × 120 = 1440 + 108 + 8 = (1556)10(c) (475)8 = 4 × 82 + 7 × 81 + 5 × 80 = 256 + 56 + 5 = (317)10(d) (2345)6 = 2 × 63 + 3 × 62 + 4 × 61 + 5 × 60 = 432 + 108 + 24 + 5 = (569)101.4 12-bit binary : 1111 1111 1111Decimal : 212 − 1 = (4095)10Hexadecimal : (FFF)161.5 Let b = base(a) 12 × 4 = 52 → (b + 2) 4 = 5b + 2(b) 75/3 = 26 4b + 8 = 5b + 2 b=6 → (7b + 5) = 3(2b + 6) 7b + 5 = 6b +18 b = 13Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.

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3(c) (2 × b + 4) + (b + 7) = 4b, so b = 111.6 x2 – 13x + 32 = 0(x – 5)(x – 4) = 0x2 – (5 + 4)x + 5 × 4 = x2 – 13x + 32So, 5 + 4 = b + 3 5 × 4 = 3b + 2b = 6 OR b=61.7 (ABCD)16 = (1010 1011 1100 1101)2 = 1 010 101 111 001 101 1 25 715 = (125715)81.8 (a) Converting (512)10 to binary is by repeated division by 2. 2 512 2 256 – 02 128 – 0 ⇒ (1000000000)2 2 64 – 0 2 32 – 0 2 16 – 0 2 8 –0 2 4 –0 2 2 –0 1 –0(b) (512)10 to hexadecimal is repeated division by 16. 16 51216 32 – 0 ⇒ (200)16 2 –0 ⇓ replace each digit by binary To binary (200)16 = (10 0000 0000)22nd method is faster.1.9 (a) (11010.0101)2 = 16 + 8 + 2 + 0.25 + 0.0625 = (26.3125)10(b) (A6.5)16 = 10 × 16 + 6 + 5 × 0.0625 = (166.3125)10(c) (276.24)8 = 2 × 82 + 7 × 8 + 6 + 2 + 4 8 64Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. https://phillylucky.netlify.app/iphone-4-hacktivate.html. M.D. Ciletti, Copyright 2012, All rights reserved.

Morris Mano Solutions Pdf

4(d) (BABA.B)16 = 128 + 56 + 6 + 0.25 + 0.0625(e) 10110.1101 = (190.3125)10 = 11 × 163 + 10 × 162 + 11 × 161 + 10 + 11 16 = 45056 + 2560 + 176 + 10 + 0.6875 = (47802.6875)10 = 16 + 4 + 2 + 0.5 + 0.25 + 0.0625 = (22.8125)10 91.10 (a) 1.100102 = 0001.10012 = 1.916 = 1 + 16 = 1.56310(b) (1100.010)2 = (C.4)16 = 12 + 4 = (12.25)10 16Shifted to left by 3 places.1.11 1010.1 110 | 111111 110111 ⇒ (1010.1)2 110 110 110 01.12 (a) (1100)2 1100 × 110 +(110)2 0000 (10010)2 1100+ 1100+ (b) (AB)16 +(1C)16 (1001000)2 (C7)16 AB × 1C 804 AB+ (12B4)161.13 (a) (35.125)10 = (100011.001)22 35 0.125 × 2 = 0.252 17 – 1 0.25 × 2 = 0.52 8 –1 0.5 × 2 = 1.02 4 –02 2 –0 1 –0Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.

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5(b) 1 = 0.33333333 3 = (0.01010101)2 ⇒ (0.33203125)10(c) (0.01010101)2 = (0.55)16 55 =+ 16 256 = (0.33203125)10Answer is same.1.14 (a) 1111 0000 (b) 0000 0000 (c) 1101 1000 1’s comp:0000 1111 1’s comp: 1111 1111 1’s comp: 0010 0111 2’s comp: 0001 0000 2’s comp: 0000 0000 2’s comp: 0010 1000(d) 0101 0101 (e) 1000 0000 (f) 1111 1111 1’s comp:1010 1010 1’s comp: 0111 1111 1’s comp: 0000 0000 2’s comp:1010 1011 2’s comp: 1000 0000 2’s comp: 0000 00011.15 (a) 25,918,036 (b) 99,999,999 9’s comp : 74,081,963 9’s comp : 00,000,000 10’s comp : 74,081,964 10’s comp : 00,000,001(c) 25,000,000 (d) 00000000 9’s comp : 74,999,999 9’s comp : 99999999 10’s comp : 75,000,000 10’s comp : 1000000001.16 (a) (CAD9)16 16’s comp: (3527)16(b) (CAD9)16 = (1100 1010 1101 1001)2(c) 1100 1010 1101 1001 0011 0101 0010 0110 1’s comp: 0011 0101 0010 0111 2’s comp:(d) 0011 0101 0010 0111 = (3527)16(a) and (d) both are same.1.17 (a) 2579 3699 +7421 9’s comp : 7420 1 1120 10’s comp : 7421 Ans: 1120 drop (b) 1800 974 9’s comp : 8199 +8200Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.


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610’s comp : 8200 9174 ⇒ –826(c) 4361 2943 9’s comp : 5638 +5639 10’s comp : 5639 8582 ⇒ − 1418(d) 0745 7631 Ans: 6886 9’s comp : 9254 +9255 10’s comp : 9255 1 6886 drop1.18 10101 Ans: 00011 (a) 10010 +01110 1’s comp : 01101 2’s comp : 01110 1 00011 drop(b) 100110 010010 1’s comp : 011001 +0110102’s comp : 011010 101100 ⇒ −010100(c) 110101 010011 1’s comp : 001010 +001011 2’s comp : 001011 011110 ⇒ −100010(d) 101101 101000 1’s comp : 010010 +010011 2’s comp : 010011 111011 ⇒ −0001011.19 +9081 → 009081 +954 → 000954 –9081 → 990918 (9’s comp) –954 → 999045 (9’s comp) –9081 → 990919 (10’s comp) –954 → 999046 (10’s comp)(a) (+9081) + (954) = 009081 + 000954 = 010035(b) (+9081) + (–954) = 009081 + 999046Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.

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7 = 008127 drop 1(c) (–9081) + (+954) = 990919 + 000954 = 991873 ⇒ –8127(d) (–9081) + (–954) = 990919 + 999046 = 989965 ⇒ –10035 1 drop1.20 +56 → 0 111000 +35 → 0 100011 –56 → 1 001000 −35 → 1 011101(a) (+56) + (+35) ⇒ 0 111000 +0 100011 (overflow) 1 0110111011011 → 91(b) (+56) + (–35) ⇒ 0 111000 +1 011101 0010101 ⇒ +21 1drop (c) (–56) + (+35) ⇒ 1 001000 +0 100011 1 101011 ⇒ –21 1 101011 is the 2’s complement of –21.Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. https://luckytp.netlify.app/dd-wrt-download.html. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.


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81.21 +9542 → 009542 +641 → 000641 –9542 → 990458 –641 → 999359(a) (+9542) + (+641) ⇒ 009542 + 000641 010183(b) (+9542) + (–641) ⇒ 009542 1 +999359 008901 drop(c) (−9542) + (+641) ⇒ 990458 +000641 991099 ⇒ −8901(d) (–9542) + (–641) = 990458 + 999359 989817 ⇒ −10183 1drop1.22 (7654)10 BCD: 0111 0110 0101 0100 ASCII: 0 0110111 0110110 0110101 0110100 7 65 41.23 694 0110 1001 0100+538 ⇒ + 0101 0011 1000Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.


9 1232 1011 1100 1100 0110 0110 0110 0001 0010 0011 0010 12321.24 Octal Digit 6311 6421 0 0000 0000 1 0001/0010 0001 2 0011 0010 3 0100 0011 4 0110/0101 0100 5 0111 0101 6 1000 0110/1000 7 1001/1010 1001/01111.25 (6514)10 (a) BCD : 0110 0101 0001 0100 (b) Excess 3 : 1001 1000 0100 0111 (c) 2421 : 1100 1011 0001 0100 (d) 6311 : 1000 0111 0001 01011.26 6514 9’s comp : 3485 2421 : 0011 0100 1110 1011 → ①1’s comp of : 1100 1011 0001 0100 is 0011 0100 1110 1011 → ②Hence ① and ② are some → self complementing.1.27 For a deck with 52 cards, we need 6 bits (25 = 32 < 52 < 64 = 26). Let the msb's select the suit (e.g., diamonds, hearts, clubs, spades are encoded respectively as 00, 01, 10, and 11. The remaining four bits select the 'number' of the card. Example: 0001 (ace) through 1011 (9), plus 101 through 1100 (jack, queen, king). This a jack of spades might be coded as 11 1010. (Note: only 52 out of 64 patterns are used.)1.28 G e o 1110 0101 r g e (space) 1100 0111 1110 1111 1111 0010 0110 0111 1110 0101 0010 0000 B 1100 0010 1010 11101.29 Digital Systems1.30 (a) C9: 1 100 1001 I EE: 1 110 1110 n F3: 1 111 0011 s 74: 0 111 0100 t 69: 0 110 1001 i 74: 0 111 0100 t F5: 1 111 0101 u 74: 0 111 0100 t 65: 0 110 0101 eDigital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.


10 (b) Even parity.1.31 62 + 32 = 94 printing characters1.32 bit 6 from the right1.33 0101 0110 0100 4 (a) BCD 5 6 1 4 (b) Excess-3 2 3 (c) 84-2-1 3 2 (d) Binary no. (1380)101.34 ASCII for decimal digits with even parity: 0 → 1 011 0000 1 → 0 011 0001 2 → 0 011 0010 3 → 1 011 0011 4 → 0 011 0100 5 → 1 011 0101 6 → 1 011 0110 7 → 0 011 01111.35 (a) abc a1.36 ab fb c gf g a fb gf gDigital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.

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